PD flow from netlist to GDS (floorplan, power planning, placement, optimization, CTS, routing, ECO steps, PV, Timing/SI)
Low power design
Proficient in sign-off – STA, DRC/LVS/Antenna/ERC, Power Analysis, IR/EM-Analysis, LEC, ECO (Timing and Functional)
OCV/MMMC, hierarchical designs and Xtalk/SI/EMIR
CTS constraints, skew fixing, timing fixes and optimization techniques
Tool specific expertise on synopsys and cadence environments
Prior experience with 28 nm, 14 nm and lower technology nodes
Expertise in block level and top level designs and contributed efforts in successful tape-outs in lower technologies and complex designs.
Synthesis, Timing analysis and closure